Functieomschrijving- Developing and managing UVM test benches for FPGA-based hardware designs.
- Creating and executing detailed test plans to validate the functionality of FPGA devices.
- Continuously improving verification methodologies and processes to enhance efficiency and quality.
- The design, realization, integration, and test of systems or subsystems for future products.
- Working with a focus on consumer needs and technological competitiveness, having an outside in approach for the designs you create & the knowledge you share with your team.
Functie-eisen- Proven experience with FPGA design and verification using UVM and System Verilog.
- A Bachelor or Master Degree in Electrical Engineering, Informatics, Computer Science or equivalent.
- 5+ years of experience in VHDL and Verilog coding.
- 5+ years of experience in System Verilog for verification.
- Familiarity with industry standards and best practices for FPGA verification.
ArbeidsvoorwaardenThe right candidate will be provided a challenging and varied position in a professional, high-tech environment.
An appropriate salary based on your experience and education.
Future prospects and excellent benefits are evident.
After a period of secondment and functioning properly, you can be contracted by our client.
Good secondary conditions such as a minimum of 25 holidays and 8,33% holiday allowance.
Courses to develop yourself professionally and personally via Trinamics Academy.
Discount on your healthcare and referral bonusses and fun activities.
Certain pre-employment screening checks may be part of this vacancy procedure.